#ifndef ALGA_AMD_SI_GPU_REGS_CTX_H
#define ALGA_AMD_SI_GPU_REGS_CTX_H
/*
  author Sylvain Bertrand <sylvain.bertrand@gmail.com>
  Protected by linux GNU GPLv2
  Copyright 2012-2014
*/

#ifndef __KERNEL__
#ifndef BIT
#define BIT(x) (1 << (x))
#endif
#endif

/* start of context register area: 0x28000-0x29000 */
/* from there we must use indirect MMIO or a CP because above reg MMIO size */
#define DB_RENDER_CTL				0x28000
#define		DRC_DEPTH_CLR_ENA			BIT(0)
#define		DRC_STENCIL_CLR_ENA			BIT(1)
#define		DRC_DEPTH_COPY				BIT(2)
#define		DRC_STENCIL_COPY			BIT(3)
#define		DRC_RESUMMARIZE_ENA			BIT(4)
#define		DRC_STENCIL_COMPRESS_DIS		BIT(5)
#define		DRC_DEPTH_COMPRESS_DIS			BIT(6)
#define		DRC_COPY_CENTROID			BIT(7)
#define		DRC_COPY_SAMPLE				0x00000f00
#define DB_CNT_CTL				0x28004
#define		DCC_ZPASS_INCREMENT_DIS			BIT(0)
#define		DCC_PERFECT_INCREMENT_DIS		BIT(1)
#define		DCC_SAMPLE_RATE				0x00000070
#define DB_DEPTH_VIEW				0x28008
#define		DDV_SLICE_START				0x000007ff
#define		DDV_SLICE_MAX				0x00ffe000
#define		DDV_Z_RD_ONLY				BIT(24)
#define		DDV_STENCIL_RD_ONLY			BIT(25)
#define DB_RENDER_OVERRIDE_0			0x2800c
#define		DRO_FORCE_HIZ_ENA			0x00000003
#define			DRO_FORCE_OFF				0
#define			DRO_FORCE_ENA				1
#define			DRO_FORCE_DIS				2
#define			DRO_FORCE_RSVD				3
#define		DRO_FORCE_HIS_ENA_0			0x0000000c
#define			DRO_FORCE_OFF				0
#define			DRO_FORCE_ENA				1
#define			DRO_FORCE_DIS				2
#define			DRO_FORCE_RSVD				3
#define		DRO_FORCE_HIS_ENA_1			0x00000030
#define			DRO_FORCE_OFF				0
#define			DRO_FORCE_ENA				1
#define			DRO_FORCE_DIS				2
#define			DRO_FORCE_RSVD				3
#define		DRO_FORCE_SHADER_Z_ORDER		BIT(6)
#define		DRO_FAST_Z_DISABLE			BIT(7)
#define		DRO_FAST_STENCIL_DIS			BIT(8)
#define		DRO_NOOP_CULL_DIS			BIT(9)
#define		DRO_FORCE_COLOR_KILL			BIT(10)
#define		DRO_FORCE_Z_RD				BIT(11)
#define		DRO_FORCE_STENCIL_RD			BIT(12)
#define		DRO_FORCE_FULL_Z_RNG			0x00006000
#define			DRO_FORCE_OFF				0
#define			DRO_FORCE_ENA				1
#define			DRO_FORCE_DIS				2
#define			DRO_FORCE_RSVD				3
#define		DRO_FORCE_QC_SMASK_CONFLICT		BIT(15)
#define		DRO_VIEWPORT_CLAMP_DIS			BIT(16)
#define		DRO_SC_ZRANGE_IGNORE			BIT(17)
#define		DRO_FULLY_COVERED_DIS			BIT(18)
#define		DRO_FORCE_Z_LIMIT_SUMM			0x00180000
#define			DRO_FORCE_SUMM_OFF			0
#define			DRO_FORCE_SUMM_MINZ			1
#define			DRO_FORCE_SUMM_MAXZ			2
#define			DRO_FORCE_SUMM_BOTH			3
#define		DRO_TILES_IN_DTT_MAX			0x03700000
#define		DRO_TILE_RATE_TILES_DIS			BIT(26)
#define		DRO_FORCE_Z_DIRTY			BIT(27)
#define		DRO_FORCE_STENCIL_DIRTY			BIT(28)
#define		DRO_FORCE_Z_VALID			BIT(29)
#define		DRO_FORCE_STENCIL_VALID			BIT(30)
#define		DRO_PRESERVE_COMPRESSION		BIT(31)
#define DB_RENDER_OVERRIDE_1			0x28010
#define		DRO_PARTIAL_SQUAD_LAUNCH_CTL		0x00000003
#define			DRO_AUTO				0
#define			DRO_ON_HANG_ONLY			1
#define			DRO_ASAP				2
#define			DRO_COUNTDOWN				3
#define		DRO_PARTIAL_SQUAD_LAUNCH_CNTDWN		0x0000001c
#define		DRO_ZMASK_EXPCLEAR_OPTIM_DIS		BIT(5)
#define		DRO_SMEM_EXPCLEAR_OPTIM_DIS		BIT(6)
#define		DRO_COLOR_ON_VALIDATION_DIS		BIT(7)
#define		DRO_DECOMPRESS_Z_ON_FLUSH		BIT(8)
#define		DRO_REG_SNOOP_DIS			BIT(9)
#define		DRO_DEPTH_BOUNDS_HIER_DEPTH_DIS		BIT(10)
#define DB_HTILE_DATA_BASE			0x28014

#define DB_DEPTH_BOUNDS_MIN			0x28020
#define DB_DEPTH_BOUNDS_MAX			0x28024
#define DB_STENCIL_CLR				0x28028
#define		DSC_CLR					0x000000ff
#define DB_DEPTH_CLR				0x2802c

#define PA_SC_SCREEN_SCISSOR_TL			0x28030
#define		PSSST_X					0x00007fff
#define		PSSST_Y					0x7fff0000
#define PA_SC_SCREEN_SCISSOR_BR			0x28034
#define		PSSSB_X					0x00007fff
#define		PSSSB_Y					0x7fff0000

#define DB_DEPTH_INFO				0x2803c
#define		DDI_ADDR5_SWIZZLE_MASK			0x0000000f
#define DB_Z_INFO				0x28040
#define		DZI_FMT					0x00000003
#define			DZI_Z_INVALID				0
#define			DZI_Z_16				1
#define			DZI_Z_24				2 /*obsolete*/
#define			DZI_Z_32_FLOAT				3
#define		DZI_SAMPLES_N				0x0000000c
#define		DZI_TILE_MODE_IDX			0x00700000
#define		DZI_ALLOW_EXP_CLR			BIT(27)
#define		DZI_READ_SZ				BIT(28)
#define		DZI_TILE_SURF_ENA			BIT(29)
#define		DZI_Z_RNG_PRECISION			BIT(31)

#define DB_STENCIL_INFO				0x28044
#define		DSI_FMT					BIT(0)
#define		DSI_TILE_MODE_IDX                       0x00700000
#define		DSI_ALLOW_EXP_CLR                       BIT(27)
#define		DSI_TILE_STENCIL_DIS			BIT(29)

#define PA_SC_WND_OF				0x28200
#define		PSWO_WND_X_OF				0x0000ffff
#define		PSWO_WND_Y_OF				0xffff0000
#define PA_SC_WND_SCISSOR_TL			0x28204
#define		PSWST_X					0x00007fff
#define		PSWST_Y					0x7fff0000
#define		PSWST_WND_OF_DIS			BIT(31)
#define PA_SC_WND_SCISSOR_BR			0x28208
#define		PSWSB_X					0x00007fff
#define		PSWSB_Y					0x7fff0000
#define		PSWSB_WND_OF_DIS			BIT(31)

#define PA_SC_CLIPRECT_RULE			0x2820c
#define		PSCR_CLIP_RULE				0x0000ffff
#define PA_SC_CLIPRECT_0_TL			0x28210
#define		PSCT_X					0x00007fff
#define		PSCT_Y					0x7fff0000
#define PA_SC_CLIPRECT_0_BR			0x28214
#define		PSCB_X					0x00007fff
#define		PSCB_Y					0x7fff0000
#define PA_SC_CLIPRECT_1_TL			0x28218
#define PA_SC_CLIPRECT_1_BR			0x2821c
#define PA_SC_CLIPRECT_2_TL			0x28220
#define PA_SC_CLIPRECT_2_BR			0x28224
#define PA_SC_CLIPRECT_3_TL			0x28228
#define PA_SC_CLIPRECT_3_BR			0x2822c
#define PA_SC_EDGERULE				0x28230
#define		PSE_ER_TRI				0x0000000f
#define		PSE_ER_POINT				0x000000f0
#define		PSE_ER_RECT				0x00000f00
#define		PSE_ER_LINE_LR				0x0003f000
#define		PSE_ER_LINE_RL				0x00fc0000
#define		PSE_ER_LINE_TB				0x0f000000
#define		PSE_ER_LINE_BT				0xf0000000
#define PA_SU_HW_SCR_OF				0x28234
#define		PSHSO_X_OF				0x000001ff
#define		PSHSO_Y_OF				0x01ff0000
#define CB_TGT_MASK				0x28238
#define		CTM_TGT_0_ENA				0x0000000f
#define			CTM_TGT_RED				0x1
#define			CTM_TGT_GREEN				0x2
#define			CTM_TGT_BLUE				0x4
#define			CTM_TGT_ALPHA				0x8
#define		CTM_TGT_1_ENA				0x000000f0
#define		CTM_TGT_2_ENA				0x00000f00
#define		CTM_TGT_3_ENA				0x0000f000
#define		CTM_TGT_4_ENA				0x000f0000
#define		CTM_TGT_5_ENA				0x00f00000
#define		CTM_TGT_6_ENA				0x0f000000
#define		CTM_TGT_7_ENA				0xf0000000
#define CB_SH_MASK				0x2823c
#define		CSM_OUTPUT_0_ENA			0x0000000f
#define			CSM_OUTPUT_RED				0x1
#define			CSM_OUTPUT_GREEN			0x2
#define			CSM_OUTPUT_BLUE				0x4
#define			CSM_OUTPUT_ALPHA			0x8
#define		CSM_OUTPUT_1_ENA			0x000000f0
#define		CSM_OUTPUT_2_ENA			0x00000f00
#define		CSM_OUTPUT_3_ENA			0x0000f000
#define		CSM_OUTPUT_4_ENA			0x000f0000
#define		CSM_OUTPUT_5_ENA			0x00f00000
#define		CSM_OUTPUT_6_ENA			0x0f000000
#define		CSM_OUTPUT_7_ENA			0xf0000000
#define PA_SC_GENERIC_SCISSOR_TL		0x28240
#define		PSGST_X					0x00007fff
#define		PSGST_Y					0x7fff0000
#define		PSGST_WND_OF_DIS			BIT(31)
#define PA_SC_GENERIC_SCISSOR_BR		0x28244
#define		PSGSB_X					0x00007fff
#define		PSGSB_Y					0x7fff0000
#define		PSGSB_WND_OF_DIS			BIT(31)


#define PA_SC_VPORT_0_SCISSOR_TL		0x28250
#define		PSVST_X					0x00007fff
#define		PSVST_Y					0x7fff0000
#define		PSVST_WND_OF_DIS			BIT(31)
#define PA_SC_VPORT_0_SCISSOR_BR		0x28254
#define		PSVSB_X					0x00007fff
#define		PSVSB_Y					0x7fff0000
#define		PSVSB_WND_OF_DIS			BIT(31)
#define PA_SC_VPORT_1_SCISSOR_TL		0x28258
#define PA_SC_VPORT_1_SCISSOR_BR		0x2825c
#define PA_SC_VPORT_2_SCISSOR_TL		0x28260
#define PA_SC_VPORT_2_SCISSOR_BR		0x28264
#define PA_SC_VPORT_3_SCISSOR_TL		0x28268
#define PA_SC_VPORT_3_SCISSOR_BR		0x2826c
#define PA_SC_VPORT_4_SCISSOR_TL		0x28270
#define PA_SC_VPORT_4_SCISSOR_BR		0x28274
#define PA_SC_VPORT_5_SCISSOR_TL		0x28278
#define PA_SC_VPORT_5_SCISSOR_BR		0x2827c
#define PA_SC_VPORT_6_SCISSOR_TL		0x28280
#define PA_SC_VPORT_6_SCISSOR_BR		0x28284
#define PA_SC_VPORT_7_SCISSOR_TL		0x28288
#define PA_SC_VPORT_7_SCISSOR_BR		0x2828c
#define PA_SC_VPORT_8_SCISSOR_TL		0x28290
#define PA_SC_VPORT_8_SCISSOR_BR		0x28294
#define PA_SC_VPORT_9_SCISSOR_TL		0x28298
#define PA_SC_VPORT_9_SCISSOR_BR		0x2829c
#define PA_SC_VPORT_A_SCISSOR_TL		0x282a0
#define PA_SC_VPORT_A_SCISSOR_BR		0x282a4
#define PA_SC_VPORT_B_SCISSOR_TL		0x282a8
#define PA_SC_VPORT_B_SCISSOR_BR		0x282ac
#define PA_SC_VPORT_C_SCISSOR_TL		0x282b0
#define PA_SC_VPORT_C_SCISSOR_BR		0x282b4
#define PA_SC_VPORT_D_SCISSOR_TL		0x282b8
#define PA_SC_VPORT_D_SCISSOR_BR		0x282bc
#define PA_SC_VPORT_E_SCISSOR_TL		0x282c0
#define PA_SC_VPORT_E_SCISSOR_BR		0x282c4
#define PA_SC_VPORT_F_SCISSOR_TL		0x282c8
#define PA_SC_VPORT_F_SCISSOR_BR		0x282cc
#define PA_SC_VPORT_0_TE_ZMIN			0x282d0
#define PA_SC_VPORT_0_TE_ZMAX			0x282d4
#define PA_SC_VPORT_1_TE_ZMIN			0x282d8
#define PA_SC_VPORT_1_TE_ZMAX			0x282dc
#define PA_SC_VPORT_2_TE_ZMIN			0x282e0
#define PA_SC_VPORT_2_TE_ZMAX			0x282e4
#define PA_SC_VPORT_3_TE_ZMIN			0x282e8
#define PA_SC_VPORT_3_TE_ZMAX			0x282ec
#define PA_SC_VPORT_4_TE_ZMIN			0x282f0
#define PA_SC_VPORT_4_TE_ZMAX			0x282f4
#define PA_SC_VPORT_5_TE_ZMIN			0x282f8
#define PA_SC_VPORT_5_TE_ZMAX			0x282fc
#define PA_SC_VPORT_6_TE_ZMIN			0x28300
#define PA_SC_VPORT_6_TE_ZMAX			0x28304
#define PA_SC_VPORT_7_TE_ZMIN			0x28308
#define PA_SC_VPORT_7_TE_ZMAX			0x2830c
#define PA_SC_VPORT_8_TE_ZMIN			0x28310
#define PA_SC_VPORT_8_TE_ZMAX			0x28314
#define PA_SC_VPORT_9_TE_ZMIN			0x28318
#define PA_SC_VPORT_9_TE_ZMAX			0x2831c
#define PA_SC_VPORT_A_TE_ZMIN			0x28320
#define PA_SC_VPORT_A_TE_ZMAX			0x28324
#define PA_SC_VPORT_B_TE_ZMIN			0x28328
#define PA_SC_VPORT_B_TE_ZMAX			0x2832c
#define PA_SC_VPORT_C_TE_ZMIN			0x28330
#define PA_SC_VPORT_C_TE_ZMAX			0x28334
#define PA_SC_VPORT_D_TE_ZMIN			0x28338
#define PA_SC_VPORT_D_TE_ZMAX			0x2833c
#define PA_SC_VPORT_E_TE_ZMIN			0x28340
#define PA_SC_VPORT_E_TE_ZMAX			0x28344
#define PA_SC_VPORT_F_TE_ZMIN			0x28348
#define PA_SC_VPORT_F_TE_ZMAX			0x2834c
#define PA_SC_RASTER_CFG			0x28350
#define		PSRC_RB_MAP_PKR_0			0x00000003
#define			PSRC_RB_MAP_0				0
#define			PSRC_RB_MAP_1				1
#define			PSRC_RB_MAP_2				2
#define			PSRC_RB_MAP_3				3
#define		PSRC_RB_MAP_PKR_1			0x0000000c
#define		PSRC_RB_XSEL_2				0x00000030
#define			PSRC_RB_XSEL_2_0			0
#define			PSRC_RB_XSEL_2_1			1
#define			PSRC_RB_XSEL_2_2			2
#define			PSRC_RB_XSEL_2_3			3
#define		PSRC_RB_XSEL				BIT(6)
#define		PSRC_RB_YSEL				BIT(7)
#define		PSRC_PKR_MAP				0x00000300
#define			PSRC_PKR_MAP_0				0
#define			PSRC_PKR_MAP_1				1
#define			PSRC_PKR_MAP_2				2
#define			PSRC_PKR_MAP_3				3
#define		PSRC_PKR_XSEL				0x00000c00
#define			PSRC_PKR_XSEL_0				0
#define			PSRC_PKR_XSEL_1				1
#define			PSRC_PKR_XSEL_2				2
#define			PSRC_PKR_XSEL_3				3
#define		PSRC_PKR_YSEL				0x00003000
#define			PSRC_PKR_YSEL_0				0
#define			PSRC_PKR_YSEL_1				1
#define			PSRC_PKR_YSEL_2				2
#define			PSRC_PKR_YSEL_3				3
#define		PSRC_SC_MAP				0x00030000
#define			PSRC_SC_MAP_0				0
#define			PSRC_SC_MAP_1				1
#define			PSRC_SC_MAP_2				2
#define			PSRC_SC_MAP_3				3
#define		PSRC_SC_XSEL				0x000c0000
#define			PSRC_SC_XSEL_8_WIDE_TILE		0
#define			PSRC_SC_XSEL_16_WIDE_TILE		1
#define			PSRC_SC_XSEL_32_WIDE_TILE		2
#define			PSRC_SC_XSEL_64_WIDE_TILE		3
#define		PSRC_SC_YSEL				0x00300000
#define			PSRC_SC_YSEL_8_WIDE_TILE		0
#define			PSRC_SC_YSEL_16_WIDE_TILE		1
#define			PSRC_SC_YSEL_32_WIDE_TILE		2
#define			PSRC_SC_YSEL_64_WIDE_TILE		3
#define		PSRC_SE_MAP				0x03000000
#define			PSRC_SE_MAP_0				0
#define			PSRC_SE_MAP_1				1
#define			PSRC_SE_MAP_2				2
#define			PSRC_SE_MAP_3				3
#define		PSRC_SE_XSEL				0x0c000000
#define			PSRC_SE_XSEL_8_WIDE_TILE		0
#define			PSRC_SE_XSEL_16_WIDE_TILE		1
#define			PSRC_SE_XSEL_32_WIDE_TILE		2
#define			PSRC_SE_XSEL_64_WIDE_TILE		3
#define		PSRC_SE_YSEL				0x30000000
#define			PSRC_SE_YSEL_8_WIDE_TILE		0
#define			PSRC_SE_YSEL_16_WIDE_TILE		1
#define			PSRC_SE_YSEL_32_WIDE_TILE		2
#define			PSRC_SE_YSEL_64_WIDE_TILE		3

#define CP_PERFMON_CTX_CTL			0x28360
#define CP_RING_ID				0x28364
#define CP_VM_ID				0x28368

#define VGT_MAX_VTX_IDX				0x28400
#define VGT_MIN_VTX_IDX				0x28404
#define VGT_IDX_OF				0x28408
#define VGT_MULTI_PRIM_IB_RESET_IDX		0x2840c

#define CB_BLEND_RED				0x28414
#define CB_BLEND_GREEN				0x28418
#define CB_BLEND_BLUE				0x2841c
#define CB_BLEND_ALPHA				0x28420

#define DB_STENCIL_CTL				0x2842c
#define		DSC_STENCILFAIL				0x0000000f
#define			DSC_STENCIL_KEEP			0x0
#define			DSC_STENCIL_ZERO			0x1
#define			DSC_STENCIL_ONES			0x2
#define			DSC_STENCIL_REPLACE_TEST		0x3
#define			DSC_STENCIL_REPLACE_OP			0x4
#define			DSC_STENCIL_ADD_CLAMP			0x5
#define			DSC_STENCIL_SUB_CLAMP			0x6
#define			DSC_STENCIL_INVERT			0x7
#define			DSC_STENCIL_ADD_WRAP			0x8
#define			DSC_STENCIL_SUB_WRAP			0x9
#define			DSC_STENCIL_AND				0xa
#define			DSC_STENCIL_OR				0xb
#define			DSC_STENCIL_XOR				0xc
#define			DSC_STENCIL_NAND			0xd
#define			DSC_STENCIL_NOR				0xe
#define			DSC_STENCIL_XNOR			0xf
#define		DSC_STENCILZPASS			0x000000f0
#define		DSC_STENCILZFAIL			0x00000f00
#define		DSC_STENCILFAIL_BF			0x0000f000
#define		DSC_STENCILZPASS_BF			0x000f0000
#define		DSC_STENCILZFAIL_BF			0x00f00000

#define DB_STENCILREFMASK			0x28430
#define		DS_STENCILTESTVAL			0x000000ff
#define		DS_STENCILMASK				0x0000ff00
#define		DS_STENCILWRITEMASK			0x00ff0000
#define		DS_STENCILOPVAL				0xff000000
#define DB_STENCILREFMASK_BF			0x28434

#define PA_SC_VPORT_0_TE_X_SCALE		0x2843c
#define	PA_SC_VPORT_0_TE_X_OF			0x28440
#define PA_SC_VPORT_0_TE_Y_SCALE		0x2843c
#define	PA_SC_VPORT_0_TE_Y_OF			0x28440
#define PA_SC_VPORT_0_TE_Z_SCALE		0x2843c
#define	PA_SC_VPORT_0_TE_Z_OF			0x28440

#define SPI_PS_INPUT_CTL_00			0x28644
#define		SPIC_OF					0x0000003f
#define		SPIC_DEFAULT_VAL			0x00000300
#define			SPIC_X_0_0F				0
#define		SPIC_FLAT_SHADE				BIT(10)
#define		SPIC_CYL_WRAP				0x0001e000
#define		SPIC_PT_SPRITE_TEX			BIT(17)
#define SPI_PS_INPUT_CTL_01			0x28648
#define SPI_PS_INPUT_CTL_02			0x2864c
#define SPI_PS_INPUT_CTL_03			0x28650
#define SPI_PS_INPUT_CTL_04			0x28654
#define SPI_PS_INPUT_CTL_05			0x28658
#define SPI_PS_INPUT_CTL_06			0x2865c
#define SPI_PS_INPUT_CTL_07			0x28660
#define SPI_PS_INPUT_CTL_08			0x28664
#define SPI_PS_INPUT_CTL_09			0x28668
#define SPI_PS_INPUT_CTL_0A			0x2866c
#define SPI_PS_INPUT_CTL_0B			0x28670
#define SPI_PS_INPUT_CTL_0C			0x28674
#define SPI_PS_INPUT_CTL_0D			0x28678
#define SPI_PS_INPUT_CTL_0E			0x2867c
#define SPI_PS_INPUT_CTL_0F			0x28680
#define SPI_PS_INPUT_CTL_10			0x28684
#define SPI_PS_INPUT_CTL_11			0x28688
#define SPI_PS_INPUT_CTL_12			0x2868c
#define SPI_PS_INPUT_CTL_13			0x28690
#define SPI_PS_INPUT_CTL_14			0x28694
#define SPI_PS_INPUT_CTL_15			0x28698
#define SPI_PS_INPUT_CTL_16			0x2869c
#define SPI_PS_INPUT_CTL_17			0x286a0
#define SPI_PS_INPUT_CTL_18			0x286a4
#define SPI_PS_INPUT_CTL_19			0x286a8
#define SPI_PS_INPUT_CTL_1A			0x286ac
#define SPI_PS_INPUT_CTL_1B			0x286b0
#define SPI_PS_INPUT_CTL_1C			0x286b4
#define SPI_PS_INPUT_CTL_1D			0x286b8
#define SPI_PS_INPUT_CTL_1E			0x286bc
#define SPI_PS_INPUT_CTL_1F			0x286c0
#define SPI_VS_OUT_CFG				0x286c4
#define		SVOC_VS_PARAM_EXPORT_COUNT		0x0000003e
#define		SVOC_VS_HALF_PACK			BIT(6)
#define		SVOC_VS_EXPORTS_FOG			BIT(7)
#define		SVOC_VS_OUT_FOG_VEC_ADDR		0x00001f00

#define SPI_PS_INPUT_ENA			0x286cc
#define		SPIE_PERSP_SAMPLE_ENA			BIT(0)
#define		SPIE_PERSP_CENTER_ENA			BIT(1)
#define		SPIE_PERSP_CENTROID_ENA			BIT(2)
#define		SPIE_PERSP_PULL_MODEL_ENA		BIT(3)
#define		SPIE_LINEAR_SAMPLE_ENA			BIT(4)
#define		SPIE_LINEAR_CENTER_ENA			BIT(5)
#define		SPIE_LINEAR_CENTROID_ENA		BIT(6)
#define		SPIE_LINE_STIPPLE_TEX_ENA		BIT(7)
#define		SPIE_POS_X_FLOAT_ENA			BIT(8)
#define		SPIE_POS_Y_FLOAT_ENA			BIT(9)
#define		SPIE_POS_Z_FLOAT_ENA			BIT(10)
#define		SPIE_POS_W_FLOAT_ENA			BIT(11)
#define		SPIE_FRONT_FACE_ENA			BIT(12)
#define		SPIE_ANCILLARY_ENA			BIT(13)
#define		SPIE_SAMPLE_COVERAGE_ENA		BIT(14)
#define		SPIE_POS_FIXED_PT_ENA			BIT(15)
#define SPI_PS_INPUT_ADDR			0x286d0
#define		SPIA_PERSP_SAMPLE_ENA			BIT(0)
#define		SPIA_PERSP_CENTER_ENA			BIT(1)
#define		SPIA_PERSP_CENTROID_ENA			BIT(2)
#define		SPIA_PERSP_PULL_MODEL_ENA		BIT(3)
#define		SPIA_LINEAR_SAMPLE_ENA			BIT(4)
#define		SPIA_LINEAR_CENTER_ENA			BIT(5)
#define		SPIA_LINEAR_CENTROID_ENA		BIT(6)
#define		SPIA_LINE_STIPPLE_TEX_ENA		BIT(7)
#define		SPIA_POS_X_FLOAT_ENA			BIT(8)
#define		SPIA_POS_Y_FLOAT_ENA			BIT(9)
#define		SPIA_POS_Z_FLOAT_ENA			BIT(10)
#define		SPIA_POS_W_FLOAT_ENA			BIT(11)
#define		SPIA_FRONT_FACE_ENA			BIT(12)
#define		SPIA_ANCILLARY_ENA			BIT(13)
#define		SPIA_SAMPLE_COVERAGE_ENA		BIT(14)
#define		SPIA_POS_FIXED_PT_ENA			BIT(15)
#define SPI_INTERPOL_CTL_0			0x286d4
#define		SIC_FLAT_SHADE_ENA			BIT(0)
#define		SIC_POINT_SPRITE_ENA			BIT(1)
#define		SIC_POINT_SPRITE_OVRD_X			0x0000001c
#define			SIC_POINT_SPRITE_OVRD_SEL_0		0
#define			SIC_POINT_SPRITE_OVRD_SEL_1		1
#define			SIC_POINT_SPRITE_OVRD_SEL_S		2
#define			SIC_POINT_SPRITE_OVRD_SEL_T		3
#define			SIC_POINT_SPRITE_OVRD_SEL_NONE		4
#define		SIC_POINT_SPRITE_OVRD_Y			0x000000e0
#define		SIC_POINT_SPRITE_OVRD_Z			0x00000700
#define		SIC_POINT_SPRITE_OVRD_W			0x00003800
#define		SIC_POINT_SPRITE_TOP_1			BIT(14)
#define SPI_PS_IN_CTL				0x286d8
#define		SPIC_INTERP_N				0x000003f
#define		SPIC_PARAM_GEN				BIT(6)
#define		SPIC_FOG_ADDR				BIT(7)
#define		SPIC_OPTIMIZE_DIS			BIT(14)
#define		SPIC_PASS_FOG_THROUGH_PS		BIT(15)

#define SPI_BARYC_CTL				0x286e0
#define		SBC_PERSP_CENTER_CTL			BIT(0)
#define		SBC_PERSP_CENTROID_CTL			BIT(4)
#define		SBC_LINEAR_CENTER_CTL			BIT(8)
#define		SBC_LINEAR_CENTROID_CTL			BIT(12)
#define		SBC_POS_FLOAT_LOCATION			0x00030000
#define			SBC_CALCULATE_PER_PIXEL_FLOATING_POINT_POS_AT	0
#define		SBC_POS_FLOAT_ULC			BIT(20)
#define		SBC_FRONT_FACE_ALL_BITS			BIT(24)

#define SPI_TMPRING_SZ				0x286e8
#define		STS_WAVES_N				0x00000fff
#define		STS_WAVE_SZ				0x01fff000

#define	SPI_SH_POS_FMT				0x2870c
#define		SSPF_POS_0_EXPORT_FMT			0x0000000f
#define			SSPF_NONE				0
#define			SSPF_1COMP				1
#define			SSPF_2COMP				2
#define			SSPF_4COMPRESS				3
#define			SSPF_4COMP				4
#define		SSPF_POS_1_EXPORT_FMT			0x000000f0
#define		SSPF_POS_2_EXPORT_FMT			0x00000f00
#define		SSPF_POS_3_EXPORT_FMT			0x0000f000
#define SPI_SH_Z_FMT				0x28710
#define		SSZF_Z_EXPORT_FMT			0x0000000f
#define			SSZF_ZERO				0
#define			SSZF_32_R				1
#define			SSZF_32_GR				2
#define			SSZF_32_AR				3
#define			SSZF_FP16_ABGR				4
#define			SSZF_UNORM16_ABGR			5
#define			SSZF_SNORM16_ABGR			6
#define			SSZF_UINT16_ABGR			7
#define			SSZF_SINT16_ABGR			8
#define			SSZF_32_ABGR				9
#define SPI_SH_COLOR_FMT			0x28714
#define		SSCF_COLOR_0_EXPORT_FMT			0x0000000f
#define			SSCF_ZERO				0
#define			SSCF_32_R				1
#define			SSCF_32_GR				2
#define			SSCF_32_AR				3
#define			SSCF_FP16_ABGR				4
#define			SSCF_UNORM16_ABGR			5
#define			SSCF_SNORM16_ABGR			6
#define			SSCF_UINT16_ABGR			7
#define			SSCF_SINT16_ABGR			8
#define			SSCF_32_ABGR				9
#define		SSCF_COLOR_1_EXPORT_FMT			0x000000f0
#define		SSCF_COLOR_2_EXPORT_FMT			0x00000f00
#define		SSCF_COLOR_3_EXPORT_FMT			0x0000f000
#define		SSCF_COLOR_4_EXPORT_FMT			0x000f0000
#define		SSCF_COLOR_5_EXPORT_FMT			0x00f00000
#define		SSCF_COLOR_6_EXPORT_FMT			0x0f000000
#define		SSCF_COLOR_7_EXPORT_FMT			0xf0000000

#define CB_0_BLEND_CTL				0x28780
#define		CBC_COLOR_SRC_BLEND			0x0000001f
#define			CBC_BLEND_ZERO				0x00
#define			CBC_BLEND_ONE				0x01
#define			CBC_BLEND_SRC_COLOR			0x02
#define			CBC_BLEND_ONE_MINUS_SRC_COLOR		0x03
#define			CBC_BLEND_SRC_ALPHA			0x04
#define			CBC_BLEND_ONE_MINUS_SRC_ALPHA		0x05
#define			CBC_BLEND_DST_ALPHA			0x06
#define			CBC_BLEND_ONE_MINUS_DST_ALPHA		0x07
#define			CBC_BLEND_DST_COLOR			0x08
#define			CBC_BLEND_ONE_MINUS_DST_COLOR		0x09
#define			CBC_BLEND_SRC_ALPHA_SATURATE		0x0a
#define			CBC_BLEND_CONSTANT_COLOR		0x0d
#define			CBC_BLEND_ONE_MINUS_CONSTANT_COLOR	0x0e
#define			CBC_BLEND_SRC_1_COLOR			0x0f
#define			CBC_BLEND_INV_SRC_1_COLOR		0x10
#define			CBC_BLEND_SRC_1_ALPHA			0x11
#define			CBC_BLEND_INV_SRC_1_ALPHA		0x12
#define			CBC_BLEND_CONSTANT_ALPHA		0x13
#define			CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA	0x14
#define		CBC_COLOR_COMB_FCN			0x00000e0
#define			CBC_COMB_DST_PLUS_SRC			0
#define			CBC_COMB_SRC_MINUS_DST			1
#define			CBC_COMB_MIN_DST_SRC			2
#define			CBC_COMB_MAX_DST_SRC			3
#define			CBC_COMB_DST_MINUS_SRC			4
#define		CBC_COLOR_DST_BLEND			0x00001f00
#define			CBC_BLEND_ZERO				0x00
#define			CBC_BLEND_ONE				0x01
#define			CBC_BLEND_SRC_COLOR			0x02
#define			CBC_BLEND_ONE_MINUS_SRC_COLOR		0x03
#define			CBC_BLEND_SRC_ALPHA			0x04
#define			CBC_BLEND_ONE_MINUS_SRC_ALPHA		0x05
#define			CBC_BLEND_DST_ALPHA			0x06
#define			CBC_BLEND_ONE_MINUS_DST_ALPHA		0x07
#define			CBC_BLEND_DST_COLOR			0x08
#define			CBC_BLEND_ONE_MINUS_DST_COLOR		0x09
#define			CBC_BLEND_SRC_ALPHA_SATURATE		0x0a
#define			CBC_BLEND_CONSTANT_COLOR		0x0d
#define			CBC_BLEND_ONE_MINUS_CONSTANT_COLOR	0x0e
#define			CBC_BLEND_SRC_1_COLOR			0x0f
#define			CBC_BLEND_INV_SRC_1_COLOR		0x10
#define			CBC_BLEND_SRC_1_ALPHA			0x11
#define			CBC_BLEND_INV_SRC_1_ALPHA		0x12
#define			CBC_BLEND_CONSTANT_ALPHA		0x13
#define			CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA	0x14
#define		CBC_COLOR_ALPHA_SRC_BLEND		0x001f0000
#define			CBC_BLEND_ZERO				0x00
#define			CBC_BLEND_ONE				0x01
#define			CBC_BLEND_SRC_COLOR			0x02
#define			CBC_BLEND_ONE_MINUS_SRC_COLOR		0x03
#define			CBC_BLEND_SRC_ALPHA			0x04
#define			CBC_BLEND_ONE_MINUS_SRC_ALPHA		0x05
#define			CBC_BLEND_DST_ALPHA			0x06
#define			CBC_BLEND_ONE_MINUS_DST_ALPHA		0x07
#define			CBC_BLEND_DST_COLOR			0x08
#define			CBC_BLEND_ONE_MINUS_DST_COLOR		0x09
#define			CBC_BLEND_SRC_ALPHA_SATURATE		0x0a
#define			CBC_BLEND_CONSTANT_COLOR		0x0d
#define			CBC_BLEND_ONE_MINUS_CONSTANT_COLOR	0x0e
#define			CBC_BLEND_SRC_1_COLOR			0x0f
#define			CBC_BLEND_INV_SRC_1_COLOR		0x10
#define			CBC_BLEND_SRC_1_ALPHA			0x11
#define			CBC_BLEND_INV_SRC_1_ALPHA		0x12
#define			CBC_BLEND_CONSTANT_ALPHA		0x13
#define			CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA	0x14
#define		CBC_ALPHA_COMB_FCN			0x00e00000
#define			CBC_COMB_DST_PLUS_SRC			0
#define			CBC_COMB_SRC_MINUS_DST			1
#define			CBC_COMB_MIN_DST_SRC			2
#define			CBC_COMB_MAX_DST_SRC			3
#define			CBC_COMB_DST_MINUS_SRC			4
#define		CBC_ALPHA_DST_BLEND			0x1f000000
#define			CBC_BLEND_ZERO				0x00
#define			CBC_BLEND_ONE				0x01
#define			CBC_BLEND_SRC_COLOR			0x02
#define			CBC_BLEND_ONE_MINUS_SRC_COLOR		0x03
#define			CBC_BLEND_SRC_ALPHA			0x04
#define			CBC_BLEND_ONE_MINUS_SRC_ALPHA		0x05
#define			CBC_BLEND_DST_ALPHA			0x06
#define			CBC_BLEND_ONE_MINUS_DST_ALPHA		0x07
#define			CBC_BLEND_DST_COLOR			0x08
#define			CBC_BLEND_ONE_MINUS_DST_COLOR		0x09
#define			CBC_BLEND_SRC_ALPHA_SATURATE		0x0a
#define			CBC_BLEND_CONSTANT_COLOR		0x0d
#define			CBC_BLEND_ONE_MINUS_CONSTANT_COLOR	0x0e
#define			CBC_BLEND_SRC_1_COLOR			0x0f
#define			CBC_BLEND_INV_SRC_1_COLOR		0x10
#define			CBC_BLEND_SRC_1_ALPHA			0x11
#define			CBC_BLEND_INV_SRC_1_ALPHA		0x12
#define			CBC_BLEND_CONSTANT_ALPHA		0x13
#define			CBC_BLEND_ONE_MINUS_CONSTANT_ALPHA	0x14
#define		CBC_SEPARATE_ALPHA_BLEND		BIT(29)
#define		CBC_CB_BLEND_ENA			BIT(30)
#define		CBC_ROP3_DIS				BIT(31)
#define CB_1_BLEND_CTL				0x28784
#define CB_2_BLEND_CTL				0x28788
#define CB_3_BLEND_CTL				0x2878c
#define CB_4_BLEND_CTL				0x28790
#define CB_5_BLEND_CTL				0x28794
#define CB_6_BLEND_CTL				0x28798
#define CB_7_BLEND_CTL				0x2879c

#define VGT_DRAW_INITIATOR			0x287f0
#define		VDI_SRC_SELECT				0x00000003
#define			VDI_DMA					0
#define			VDI_IMM					1
#define			VDI_AUTO_IDX				2
#define			VDI_RSVED				3
#define		VDI_MAJOR_MODE				0x0000000c
#define			VDI_0					0
#define			VDI_1					1
#define		VDI_NOT_EOP				BIT(5)
#define		VDI_USE_OPAQUE				BIT(6)

#define DB_DEPTH_CTL				0x28800
#define		DDC_STENCIL_ENA				BIT(0)
#define		DDC_Z_ENA				BIT(1)
#define		DDC_Z_WRITE_ENA				BIT(2)
#define		DDC_DEPTH_BOUNDS_ENA			BIT(3)
#define		DDC_ZFUNC				0x00000070			
#define			DDC_ZFUNC_NEVER				0
#define			DDC_ZFUNC_LESS				1
#define			DDC_ZFUNC_EQUAL				2
#define			DDC_ZFUNC_LEQUAL			3
#define			DDC_ZFUNC_GREATER			4
#define			DDC_ZFUNC_NOTEQUAL			5
#define			DDC_ZFUNC_GEQUAL			6
#define			DDC_ZFUNC_ALWAYS			7
#define		DDC_BACKFACE_ENA			BIT(7)
#define		DDC_STENCILFUNC				0x00000700
#define			DDC_STENCILFUNC_NEVER			0
#define			DDC_STENCILFUNC_LESS			1
#define			DDC_STENCILFUNC_EQUAL			2
#define			DDC_STENCILFUNC_LEQUAL			3
#define			DDC_STENCILFUNC_GREATER			4
#define			DDC_STENCILFUNC_NOTEQUAL		5
#define			DDC_STENCILFUNC_GEQUAL			6
#define			DDC_STENCILFUNC_ALWAYS			7
#define		DDC_STENCILFUNC_BF			0x00700000
#define		DDC_COLOR_WRITES_ON_DEPTH_FAIL_ENA	BIT(30)
#define		DDC_COLOR_WRITES_ON_DEPTH_PASS_DIS	BIT(31)
#define DB_EQAA					0x28804
#define CB_COLOR_CTL				0x28808
#define		CCC_DEGAMMA_ENA				BIT(3)
#define		CCC_MODE				0x00000070
#define			CCC_CB_DISABLE				0
#define			CCC_CB_NORMAL				1
#define			CCC_CB_ELIMINATE_FAST_CLR		2
#define			CCC_CB_RESOLVE				3
#define			CCC_CB_FMASK_DECOMPRESS			5
#define		CCC_ROP3				0x00ff0000
#define			CCC_0X00				0x00
#define			CCC_0X05				0x05
#define			CCC_0X0A				0x0a
#define			CCC_0X0F				0x0f
#define			CCC_0X11				0x11
#define			CCC_0X22				0x22
#define			CCC_0X33				0x33
#define			CCC_0X44				0x44
#define			CCC_0X50				0x50
#define			CCC_0X55				0x55
#define			CCC_0X5A				0x5a
#define			CCC_0X5F				0x5f
#define			CCC_0X66				0x66
#define			CCC_0X77				0x77
#define			CCC_0X88				0x88
#define			CCC_0X99				0x99
#define			CCC_0XA0				0xa0
#define			CCC_0XA5				0xa5
#define			CCC_0XAA				0xaa
#define			CCC_0XAF				0xaf
#define			CCC_0XBB				0xbb
#define			CCC_0XCC				0xcc
#define			CCC_0XDD				0xdd
#define			CCC_0XEE				0xee
#define			CCC_0XF0				0xf0
#define			CCC_0XF5				0xf5
#define			CCC_0XFA				0xfa
#define			CCC_0XFF				0xff
#define DB_SH_CTL				0x2880c
#define		DSC_Z_EXPORT_ENA			BIT(0)
#define		DSC_STENCIL_TEST_VAL_EXPORT_ENA		BIT(1)
#define		DSC_STENCIL_OP_VAL_EXPORT_ENA		BIT(2)
#define		DSC_Z_ORDER				0x00000030
#define			DSC_LATE_Z				0
#define			DSC_EARLY_Z_THEN_LATE_Z			1
#define			DSC_RE_Z				2
#define			DSC_EARLY_Z_THEN_RE_Z			3
#define		DSC_KILL_ENA				BIT(6)
#define		DSC_COVERAGE_TO_MASK_ENA		BIT(7)
#define		DSC_MASK_EXPORT_ENA			BIT(8)
#define		DSC_EXEC_ON_HIER_FAIL			BIT(9)
#define		DSC_EXEC_ON_NOOP			BIT(10)
#define		DSC_ALPHA_TO_MASK_DIS			BIT(11)
#define		DSC_DEPTH_BEFORE_SHADER			BIT(12)
#define PA_CL_CLIP_CTL				0x28810
#define		PCCC_UCP_ENA_0				BIT(0)
#define		PCCC_UCP_ENA_1				BIT(1)
#define		PCCC_UCP_ENA_2				BIT(2)
#define		PCCC_UCP_ENA_3				BIT(3)
#define		PCCC_UCP_ENA_4				BIT(4)
#define		PCCC_UCP_ENA_5				BIT(5)
#define		PCCC_PS_UCP_Y_SCALE_NEG			BIT(13)
#define		PCCC_PS_UCP_MODE			0x0000c000
#define		PCCC_CLIP_DIS				BIT(16)
#define		PCCC_UCP_CULL_ONLY_ENA			BIT(17)
#define		PCCC_BOUNDARY_EDGE_FLG_ENA		BIT(18)
#define		PCCC_DX_CLIP_SPACE_DEF			BIT(19)
#define		PCCC_DIS_CLIP_ERR_DETECT		BIT(20)
#define		PCCC_VTX_KILL_OR			BIT(21)
#define		PCCC_DX_RASTERIZATION_KILL		BIT(22)
#define		PCCC_DX_LINEAR_ATTR_CLIP_ENA		BIT(24)
#define		PCCC_VTE_VPORT_PROVOKE_DIS		BIT(25)
#define		PCCC_ZCLIP_NEAR_DIS			BIT(26)
#define		PCCC_ZCLIP_FAR_DIS			BIT(27)
#define PA_SU_SC_MODE_CTL			0x28814
#define		PSSMC_CULL_FRONT			BIT(0)
#define		PSSMC_CULL_BACK				BIT(1)
#define		PSSMC_FACE				BIT(2)
#define		PSSMC_POLY_MODE				0x00000018
#define			PSSMC_POLY_MODE_DIS			0
#define			PSSMC_DUAL_MODE				1
#define		PSSMC_POLY_MODE_FRONT_PTYPE		0x000000e0
#define			PSSMC_DRAW_POINTS			0
#define			PSSMC_DRAW_LINES			1
#define			PSSMC_DRAW_TRIANGLES			2
#define		PSSMC_POLY_MODE_BACK_PTYPE		0x00000700
#define			PSSMC_DRAW_POINTS			0
#define			PSSMC_DRAW_LINES			1
#define			PSSMC_DRAW_TRIANGLES			2
#define		PSSMC_POLY_OF_FRONT_ENA			BIT(11)
#define		PSSMC_POLY_OF_BACK_ENA			BIT(12)
#define		PSSMC_POLY_OF_PARA_ENA			BIT(13)
#define		PSSMC_VTX_WND_OF_ENA			BIT(16)
#define		PSSMC_PROVOKING_VTX_LAST		BIT(19)
#define		PSSMC_PERSP_CORR_DIS			BIT(20)
#define		PSSMC_MULTI_PRIM_IB_ENA			BIT(21)
#define PA_SC_VPORT_TE_CTL			0x28818
#define		PSVTC_VPORT_X_SCALE_ENA			BIT(0)
#define		PSVTC_VPORT_X_OF_ENA			BIT(1)
#define		PSVTC_VPORT_Y_SCALE_ENA			BIT(2)
#define		PSVTC_VPORT_Y_OF_ENA			BIT(3)
#define		PSVTC_VPORT_Z_SCALE_ENA			BIT(4)
#define		PSVTC_VPORT_Z_OF_ENA			BIT(5)
#define		PSVTC_VTX_XY_FMT			BIT(8)
#define		PSVTC_VTX_Z_FMT				BIT(9)
#define		PSVTC_VTX_W0_FMT			BIT(10)
#define PA_CL_VS_OUT_CTL			0x2881c
#define		PCVOC_CLIP_DIST_ENA_0			BIT(0)
#define		PCVOC_CLIP_DIST_ENA_1			BIT(1)
#define		PCVOC_CLIP_DIST_ENA_2			BIT(2)
#define		PCVOC_CLIP_DIST_ENA_3			BIT(3)
#define		PCVOC_CLIP_DIST_ENA_4			BIT(4)
#define		PCVOC_CLIP_DIST_ENA_5			BIT(5)
#define		PCVOC_CLIP_DIST_ENA_6			BIT(6)
#define		PCVOC_CLIP_DIST_ENA_7			BIT(7)
#define		PCVOC_CLIP_DIST_ENA_8			BIT(8)
#define		PCVOC_CLIP_DIST_ENA_9			BIT(9)
#define		PCVOC_CLIP_DIST_ENA_A			BIT(10)
#define		PCVOC_CLIP_DIST_ENA_B			BIT(11)
#define		PCVOC_CLIP_DIST_ENA_C			BIT(12)
#define		PCVOC_CLIP_DIST_ENA_D			BIT(13)
#define		PCVOC_CLIP_DIST_ENA_E			BIT(14)
#define		PCVOC_CLIP_DIST_ENA_F			BIT(15)
#define		PCVOC_USE_VTX_POINT_SZ			BIT(16)
#define		PCVOC_USE_VTX_EDGE_FLG			BIT(17)
#define		PCVOC_USE_VTX_RENDER_TGT_IDX		BIT(18)
#define		PCVOC_USE_VTX_VIEWPORT_IDX		BIT(19)
#define		PCVOC_USE_VTX_KILL_FLG			BIT(20)
#define		PCVOC_VS_OUT_MISC_VEC_ENA		BIT(21)
#define		PCVOC_VS_OUT_CCDIST_0_VEC_ENA		BIT(22)
#define		PCVOC_VS_OUT_CCDIST_1_VEC_ENA		BIT(23)
#define		PCVOC_VS_OUT_MISC_SIDE_BUS_ENA		BIT(24)
#define		PCVOC_USE_VTX_GS_CUT_FLAG		BIT(25)
#define PA_CL_NANINF_CTL			0x28820
#define		PCNC_VTE_XY_INF_DISCARD			BIT(0)
#define		PCNC_VTE_Z_INF_DISCARD			BIT(1)
#define		PCNC_VTE_W_INF_DISCARD			BIT(2)
#define		PCNC_VTE_0XNANINF_IS_0			BIT(3)
#define		PCNC_VTE_XY_NAN_RETAIN			BIT(4)
#define		PCNC_VTE_Z_NAN_RETAIN			BIT(5)
#define		PCNC_VTE_W_NAN_RETAIN			BIT(6)
#define		PCNC_VTE_W_RECIP_NAN_IS_0		BIT(7)
#define		PCNC_VS_XY_NAN_TO_INF			BIT(8)
#define		PCNC_VS_XY_INF_RETAIN			BIT(9)
#define		PCNC_VS_Z_NAN_TO_INF			BIT(10)
#define		PCNC_VS_Z_INF_RETAIN			BIT(11)
#define		PCNC_VS_W_NAN_TO_INF			BIT(12)
#define		PCNC_VS_W_INF_RETAIN			BIT(13)
#define		PCNC_VS_CLIP_DIST_INF_DISCARD		BIT(14)
#define		PCNC_VTE_NO_OUTPUT_NEG_0		BIT(20)
#define PA_SU_LINE_STIPPLE_CTL			0x28824
#define		PSLSC_LINE_STIPPLE_RESET		0x00000003
#define		PSLSC_EXPAND_FULL_LENGTH		BIT(2)
#define		PSLSC_FRACTIONAL_ACCUM			BIT(3)
#define		PSLSC_DIAMOND_ADJUST			BIT(4)
#define PA_SU_LINE_STIPPLE_SCALE		0x28828
#define PA_SU_PRIM_FILTER_CTL			0x2882c
#define		PSPFC_TRIANGLE_FILTER_DIS		BIT(0)
#define		PSPFC_LINE_FILTER_DIS			BIT(1)
#define		PSPFC_POINT_FILTER_DIS			BIT(2)
#define		PSPFC_RECTANGLE_FILTER_DIS		BIT(3)
#define		PSPFC_TRIANGLE_EXPAND_ENA		BIT(4)
#define		PSPFC_LINE_EXPAND_ENA			BIT(5)
#define		PSPFC_POINT_EXPAND_ENA			BIT(6)
#define		PSPFC_RECTANGLE_EXPAND_ENA		BIT(7)
#define		PSPFC_PRIM_EXPAND_CONSTANT		BIT(8)
#define SQ_LSTMP_RING_ITEM_SZ			0x28830
#define SQ_HSTMP_RING_ITEM_SZ			0x28834

#define PA_SU_POINT_SZ				0x28a00
#define		PSPS_H					0x0000ffff
#define		PSPS_W					0xffff0000
#define PA_SU_POINT_MINMAX			0x28a04
#define		PSPM_MIN				0x0000ffff
#define		PSPM_MAX				0xffff0000
#define PA_SU_LINE_CTL				0x28a08
#define		PSLC_W					0x0000ffff
#define PA_SC_LINE_STIPPLE			0x28a0c
#define		PSLS_LINE_PATTERN			0x0000ffff
#define		PSLS_REPEAT_CNT				0x00ff0000
#define		PSLS__PATTERN_BIT_ORDER			BIT(18)
#define		PSLS_AUTO_RESET_CTL			0x60000000
#define VGT_OUTPUT_PATH_CTL			0x28a10
#define		VOPC_PATH_SELECT			0x00000007
#define			VOPC_VTX_REUSE				0
#define			VOPC_TESS_ENA				1
#define			VOPC_PASSTHRU				2
#define			VOPC_GS_BLK				3
#define			VOPC_HS_BLK				4
#define VGT_HOS_CTL				0x28a14
#define		VHC_TESS_MODE				0x00000003
#define VGT_HOS_MAX_TESS_LVL			0x28a18
#define VGT_HOS_MIN_TESS_LVL			0x28a1c
#define VGT_HOS_REUSE_DEPTH			0x28a20
#define		VHRD_REUSE_DEPTH			0x000000ff
#define VGT_GROUP_PRIM_TYPE			0x28a24
#define		VGPT_PRIM_TYPE				0x0000001f
#define			VGPT_3D_POINT				0
#define			VGPT_3D_LINE				1
#define			VGPT_3D_TRI				2
#define			VGPT_3D_RECT				3
#define			VGPT_3D_QUAD				4
#define			VGPT_2D_COPY_RECT_V0			5
#define			VGPT_2D_COPY_RECT_V1			6
#define			VGPT_2D_COPY_RECT_V2			7
#define			VGPT_2D_COPY_RECT_V3			8
#define			VGPT_2D_FILL_RECT			9
#define			VGPT_2D_LINE				10
#define			VGPT_2D_TRI				11
#define			VGPT_PRIM_IDX_LINE			12
#define			VGPT_PRIM_IDX_TRI			13
#define			VGPT_PRIM_IDX_QUAD			14
#define			VGPT_3D_LINE_ADJ			15
#define			VGPT_3D_TRI_ADJ				16
#define			VGPT_3D_PATCH				17
#define		VGPT_RETAIN_ORDER			BIT(14)
#define		VGPT_RETAIN_QUADS			BIT(15)
#define		VGPT_PRIM_ORDER				0x00070000
#define			VGPT_LIST				0
#define			VGPT_STRIP				1
#define			VGPT_FAN				2
#define			VGPT_LOOP				3
#define			VGPT_POLY				4
#define VGT_GROUP_FIRST_DECR			0x28a28
#define		VGFD_FIRST_DECR				0x0000000f
#define VGT_GROUP_DECR				0x28a2c
#define		VGD_DECR				0x0000000f
#define VGT_GROUP_VECT_0_CTL			0x28a30
#define		VGVC_COMP_X_ENA				BIT(0)
#define		VGVC_COMP_Y_ENA				BIT(1)
#define		VGVC_COMP_Z_ENA				BIT(2)
#define		VGVC_COMP_W_ENA				BIT(3)
#define		VGVC_STRIDE				0x0000ff00
#define		VGVC_SHIFT				0x00ff0000
#define VGT_GROUP_VECT_1_CTL			0x28a34
#define VGT_GROUP_VECT_0_FMT_CTL		0x28a38
#define		VGVFC_X_CONV				0x0000000f
#define			VGVFC_IDX_16				0
#define			VGVFC_IDX_32				1
#define			VGVFC_UINT16				2
#define			VGVFC_UINT32				3
#define			VGVFC_SINT16				4
#define			VGVFC_SINT32				5
#define			VGVFC_FLOAT32				6
#define			VGVFC_AUTO_PRIM				7
#define			VGVFC_FIX_1_23_TO_FLOAT			8
#define		VGVFC_X_OF				0x000000f0
#define		VGVFC_Y_CONV				0x00000f00
#define		VGVFC_Y_OF				0x0000f000
#define		VGVFC_Z_CONV				0x000f0000
#define		VGVFC_Z_OF				0x00f00000
#define		VGVFC_W_CONV				0x0f000000
#define		VGVFC_W_OF				0xf0000000
#define VGT_GROUP_VECT_1_FMT_CTL		0x28a3c
#define VGT_GS_MODE				0x28a40
#define		VGS_MODE				0x00000003
#define			VGS_OFF					0
#define			VGS_SCENARIO_A				1
#define			VGS_SCENARIO_B				2
#define			VGS_SCENARIO_G				3
#define			VGS_SCENARIO_C				4
#define			VGS_SPRITE_ENA				5
#define		VGS_CUT_MODE				0x00000030
#define			VGS_CUT_1024				0
#define			VGS_CUT_512				1
#define			VGS_CUT_256				2
#define			VGS_CUT_128				3
#define		VGS_GS_C_PACK_ENA			BIT(11)
#define		VGS_ES_PASSTHRU				BIT(13)
#define		VGS_COMPUTE_MODE			BIT(14)
#define		VGS_FAST_COMPUTE_MODE			BIT(15)
#define		VGS_ELEMENT_INFO_ENA			BIT(16)
#define		VGS_PARTIAL_THD_AT_EOI			BIT(17)
#define		VGS_SUPPRESS_CUTS			BIT(18)
#define		VGS_ES_WR_OPTIM				BIT(19)
#define		VGS_GS_WR_OPTIM				BIT(20)

#define PA_SC_MODE_CTL_0			0x28a48
#define		PSMC_MSAA_ENA				BIT(0)
#define		PSMC_VPORT_SCISSOR_ENA			BIT(1)
#define		PSMC_LINE_STIPPLE_ENA			BIT(2)
#define		PSMC_SEND_UNLIT_STILES_TO_PKR		BIT(3)
#define PA_SC_MODE_CTL_1			0x28a4c
#define		PSMC_WALK_SZ				BIT(0)
#define		PSMC_WALK_ALIGNMENT			BIT(1)
#define		PSMC_WALK_ALIGN8_PRIM_FITS_ST		BIT(2)
#define		PSMC_WALK_FENCE_ENA			BIT(3)
#define		PSMC_WALK_FENCE_SZ			BIT(4)
#define		PSMC_SUPERTILE_WALK_ORDER_ENA		BIT(7)
#define		PSMC_TILE_WALK_ORDER_ENA		BIT(8)
#define		PSMC_TILE_COVER_DIS			BIT(9)
#define		PSMC_TILE_COVER_NO_SCISSOR		BIT(10)
#define		PSMC_ZMM_LINE_EXTENT			BIT(11)
#define		PSMC_ZMM_LINE_OF			BIT(12)
#define		PSMC_ZMM_RECT_EXTENT			BIT(13)
#define		PSMC_KILL_PIX_POST_HI_Z			BIT(14)
#define		PSMC_KILL_PIX_POST_DETAIL_MASK		BIT(15)
#define		PSMC_PS_ITER_SAMPLE			BIT(16)
#define		PSMC_MULTI_SHADER_ENGINE_PRIM_DISC	BIT(17)
#define		PSMC_FORCE_EOV_CNTDWN_ENA		BIT(25)
#define		PSMC_FORCE_EOV_REZ_ENA			BIT(26)
#define		PSMC_OUT_OF_ORDER_PRIM_ENA		BIT(27)
#define		PSMC_OUT_OF_ORDER_WATER_MARK		0x70000000

#define VGT_PRIM_ID_ENA				0x28a84
#define		VPIE_PRIM_ID_ENA			BIT(0)
#define		VPIE_RESET_ON_EOI_DIS			BIT(1)

#define VGT_PRIM_ID_RESET			0x28a8c
#define VGT_EVENT_INITIATOR			0x28a90
#define		VEI_EVENT_TYPE				0x0000003f
#define			VEI_SAMPLE_STREAMOUTSTATS1		0x01
#define			VEI_SAMPLE_STREAMOUTSTATS2		0x02
#define			VEI_SAMPLE_STREAMOUTSTATS3		0x03
#define			VEI_CACHE_FLUSH_TS			0x04
#define			VEI_CONTEXT_DONE			0x05
#define			VEI_CACHE_FLUSH				0x06
#define			VEI_CS_PARTIAL_FLUSH			0x07
#define			VEI_VGT_STREAMOUT_SYNC			0x08
#define			VEI_VGT_STREAMOUT_RESET			0x0a
#define			VEI_END_OF_PIPE_INCR_DE			0x0b
#define			VEI_END_OF_PIPE_IB_END			0x0c
#define			VEI_RST_PIX_CNT				0x0d
#define			VEI_VS_PARTIAL_FLUSH			0x0f
#define			VEI_PS_PARTIAL_FLUSH			0x10
#define			VEI_FLUSH_HS_OUTPUT			0x11
#define			VEI_FLUSH_LS_OUTPUT			0x12
#define			VEI_CACHE_FLUSH_AND_INV_TS_EVENT	0x14
#define			VEI_ZPASS_DONE				0x15
#define			VEI_CACHE_FLUSH_AND_INV_EVENT		0x16
#define			VEI_PERFCOUNTER_START			0x17
#define			VEI_PERFCOUNTER_STOP			0x18
#define			VEI_PIPELINESTAT_START			0x19
#define			VEI_PIPELINESTAT_STOP			0x1a
#define			VEI_PERFCOUNTER_SAMPLE			0x1b
#define			VEI_FLUSH_ES_OUTPUT			0x1c
#define			VEI_FLUSH_GS_OUTPUT			0x1d
#define			VEI_SAMPLE_PIPELINESTAT			0x1e
#define			VEI_SO_VGTSTREAMOUT_FLUSH		0x1f
#define			VEI_SAMPLE_STREAMOUTSTATS		0x20
#define			VEI_RESET_VTX_CNT			0x21
#define			VEI_BLOCK_CONTEXT_DONE			0x22
#define			VEI_CS_CONTEXT_DONE			0x23
#define			VEI_VGT_FLUSH				0x24
#define			VEI_SC_SEND_DB_VPZ			0x27
#define			VEI_BOTTOM_OF_PIPE_TS			0x28
#define			VEI_DB_CACHE_FLUSH_AND_INV		0x2a
#define			VEI_FLUSH_AND_INV_DB_DATA_TS		0x2b
#define			VEI_FLUSH_AND_INV_DB_META		0x2c
#define			VEI_FLUSH_AND_INV_CB_DATA_TS		0x2d
#define			VEI_FLUSH_AND_INV_CB_META		0x2e
#define			VEI_CS_DONE				0x2f
#define			VEI_PS_DONE				0x30
#define			VEI_FLUSH_AND_INV_CB_PIXEL_DATA		0x31
#define			VEI_THREAD_TRACE_START			0x33
#define			VEI_THREAD_TRACE_STOP			0x34
#define			VEI_THREAD_TRACE_MARKER			0x35
#define			VEI_THREAD_TRACE_FLUSH			0x36
#define			VEI_THREAD_TRACE_FINISH			0x37
#define VGT_MULTI_PRIM_IB_RESET_ENA		0x28a94
#define		VMPIRE_RESET_ENA			BIT(0)

#define VGT_INST_STEP_RATE_0			0x28aa0
#define VGT_INST_STEP_RATE_1			0x28aa4
#define IA_MULTI_VGT_PARAM			0x28aa8
#define		IMVP_PRIM_GROUP_SZ			0x0000ffff
#define		IMVP_PARTIAL_VS_WAVE_ON			BIT(16)
#define		IMVP_SWITCH_ON_EOP			BIT(17)
#define		IMVP_PARTIAL_ES_WAVE_ON			BIT(18)
#define		IMVP_SWITCH_ON_EOI			BIT(19)

#define VGT_REUSE_OFF				0x28ab4
#define		VRO_OFF					BIT(0)
#define VGT_VTX_CNT_ENA				0x28ab8
#define		VVCE_VTX_CNT_ENA			BIT(0)

#define DB_SRESULTS_CMP_STATE_0			0x28ac0
#define		DSCS_CMP_FUNC				0x00000007
#define			DSCS_REF_NEVER				0
#define			DSCS_REF_LESS				1
#define			DSCS_REF_EQUAL				2
#define			DSCS_REF_LEQUAL				3
#define			DSCS_REF_GREATER			4
#define			DSCS_REF_NOTEQUAL			5
#define			DSCS_REF_GEQUAL				6
#define			DSCS_REF_ALWAYS				7
#define		DSCS_CMP_VALUE				0x00000ff0
#define		DSCS_CMP_MASK				0x000ff000
#define		DSCS_ENABLE				BIT(24)
#define DB_SRESULTS_CMP_STATE_1			0x28ac4
#define DB_PRELOAD_CTL				0x28ac8
#define		DPC_START_X				0x000000ff
#define		DPC_START_Y				0x0000ff00
#define		DPC_MAX_X				0x00ff0000
#define		DPC_MAX_Y				0xff000000

#define VGT_SHADER_STAGES_ENA			0x28b54
#define		VSSE_LS_ENA				0x00000003
#define			VSSE_LS_STAGE_OFF			0
#define			VSSE_LS_STAGE_ON			1
#define			VSSE_CS_STAGE_ON			2
#define		VSSE_HS_ENA				BIT(2)
#define		VSSE_ES_ENA				0x00000018
#define			VSSE_ES_STAGE_OFF			0
#define			VSSE_ES_STAGE_DS			1
#define			VSSE_ES_STAGE_REAL			2
#define		VSSE_GS_ENA				BIT(5)
#define		VSSE_VS_ENA				0x000000c0
#define			VSSE_VS_STAGE_REAL			0
#define			VSSE_VS_STAGE_DS			1
#define			VSSE_VS_STAGE_COPY_SHADER		2
#define		VSSE_DYNAMIC_HS				BIT(8)

#define DB_ALPHA_TO_MASK			0x28b70
#define		DATM_ALPHA_TO_MASK_ENA			BIT(0)
#define		DATM_ALPHA_TO_MASK_OF_0			0x00000300
#define		DATM_ALPHA_TO_MASK_OF_1			0x00000c00
#define		DATM_ALPHA_TO_MASK_OF_2			0x00003000
#define		DATM_ALPHA_TO_MASK_OF_3			0x0000c000
#define		DATM_OF_ROUND				BIT(16)

#define PA_SU_POLY_OF_DB_FMT_CTL		0x28b78
#define		PSPODFC_POLY_OF_NEG_DB_BITS_N		0x000000ff
#define		PSPODFC_POLY_OF_DB_IS_FLOAT_FMT		BIT(8)
#define PA_SU_POLY_OF_CLAMP			0x28b7c
#define PA_SU_POLY_OF_FRONT_SCALE		0x28b80
#define PA_SU_POLY_OF_FRONT_OF			0x28b84
#define PA_SU_POLY_OF_BACK_SCALE		0x28b88
#define PA_SU_POLY_OF_BACK_OF			0x28b8c

#define VGT_STRMOUT_CFG				0x28b94
#define		VSC_STRMOUT_0_ENA			BIT(0)
#define		VSC_STRMOUT_1_ENA			BIT(1)
#define		VSC_STRMOUT_2_ENA			BIT(2)
#define		VSC_STRMOUT_3_ENA			BIT(3)
#define		VSC_RAST_STRM				BIT(4)
#define		VSC_RAST_STRM_MASK			BIT(8)
#define		VSC_USE_RAST_STRM_MASK			BIT(31)
#define VGT_STRMOUT_BUF_CFG			0x28b98
#define		VSBC_STRM_0_BUF_ENA			0x0000000f
#define		VSBC_STRM_1_BUF_ENA			0x000000f0
#define		VSBC_STRM_2_BUF_ENA			0x00000f00
#define		VSBC_STRM_3_BUF_ENA			0x0000f000

#define PA_SC_CENTROID_PRIORITY_0		0x28bd4
#define		PSCP_DISTANCE_0				0x0000000f
#define		PSCP_DISTANCE_1				0x000000f0
#define		PSCP_DISTANCE_2				0x00000f00
#define		PSCP_DISTANCE_3				0x0000f000
#define		PSCP_DISTANCE_4				0x000f0000
#define		PSCP_DISTANCE_5				0x00f00000
#define		PSCP_DISTANCE_6				0x0f000000
#define		PSCP_DISTANCE_7				0xf0000000
#define PA_SC_CENTROID_PRIORITY_1		0x28bd8
#define		PSCP_DISTANCE_8				0x0000000f
#define		PSCP_DISTANCE_9				0x000000f0
#define		PSCP_DISTANCE_A				0x00000f00
#define		PSCP_DISTANCE_B				0x0000f000
#define		PSCP_DISTANCE_C				0x000f0000
#define		PSCP_DISTANCE_D				0x00f00000
#define		PSCP_DISTANCE_E				0x0f000000
#define		PSCP_DISTANCE_F				0xf0000000
#define PA_SC_LINE_CTL				0x28bdc
#define		PSLC_EXPAND_LINE_W			BIT(9)
#define		PSLC_LAST_PIXEL				BIT(10)
#define		PSLC_PERPENDICULAR_ENDCAP_ENA		BIT(11)
#define		PSLC_DX10_DIAMOND_TEST_ENA		BIT(12)
#define PA_SC_AA_CFG				0x28be0
#define		PSAC_MSAA_SAMPLES_N			0x00000007
#define		PSAC_AA_MASK_CENTROID_DTMN		BIT(4)
#define		PSAC_MAX_SAMPLE_DIST			0x0001e000
#define		PSAC_MSAA_EXPOSED_SAMPLES		0x00700000
#define		PSAC_DETAIL_TO_EXPOSED_MODE		0x03000000
#define PA_SU_VTX_CTL				0x28be4
#define		PSVC_PIX_CENTER				BIT(0)
#define		PSVC_ROUND_MODE				0x00000006
#define			PSVC_TRUNCATE				0
#define			PSVC_ROUND				1
#define			PSVC_ROUND_TO_EVEN			2
#define			PSVC_ROUND_TO_ODD			3
#define		PSVC_QUANT_MODE				0x00000038
#define			PSVC_16_8_FIXED_POINT_1_16TH		0
#define			PSVC_16_8_FIXED_POINT_1_8TH		1
#define			PSVC_16_8_FIXED_POINT_1_4TH		2
#define			PSVC_16_8_FIXED_POINT_1_2		3
#define			PSVC_16_8_FIXED_POINT_1			4
#define			PSVC_16_8_FIXED_POINT_1_256T		5
#define			PSVC_14_10_FIXED_POINT_1_1024TH		6
#define			PSVC_12_12_FIXED_POINT_1_4096TH		7
#define PA_CL_GB_VERT_CLIP_ADJ			0x28be8
#define PA_CL_GB_VERT_DISC_ADJ			0x28bec
#define PA_CL_GB_HORZ_CLIP_ADJ			0x28bf0
#define PA_CL_GB_HORZ_DISC_ADJ			0x28bf4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0	0x28bf8
#define		PSASLPX_S_0_X				0x0000000f
#define		PSASLPX_S_0_Y				0x000000f0
#define		PSASLPX_S_1_X				0x00000f00
#define		PSASLPX_S_1_Y				0x0000f000
#define		PSASLPX_S_2_X				0x000f0000
#define		PSASLPX_S_2_Y				0x00f00000
#define		PSASLPX_S_3_X				0x0f000000
#define		PSASLPX_S_3_Y				0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1	0x28bfc
#define		PSASLPX_S_4_X				0x0000000f
#define		PSASLPX_S_4_Y				0x000000f0
#define		PSASLPX_S_5_X				0x00000f00
#define		PSASLPX_S_5_Y				0x0000f000
#define		PSASLPX_S_6_X				0x000f0000
#define		PSASLPX_S_6_Y				0x00f00000
#define		PSASLPX_S_7_X				0x0f000000
#define		PSASLPX_S_7_Y				0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2	0x28c00
#define		PSASLPX_S_8_X				0x0000000f
#define		PSASLPX_S_8_Y				0x000000f0
#define		PSASLPX_S_9_X				0x00000f00
#define		PSASLPX_S_9_Y				0x0000f000
#define		PSASLPX_S_A_X				0x000f0000
#define		PSASLPX_S_A_Y				0x00f00000
#define		PSASLPX_S_B_X				0x0f000000
#define		PSASLPX_S_B_Y				0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3	0x28c04
#define		PSASLPX_S_C_X				0x0000000f
#define		PSASLPX_S_C_Y				0x000000f0
#define		PSASLPX_S_D_X				0x00000f00
#define		PSASLPX_S_D_Y				0x0000f000
#define		PSASLPX_S_E_X				0x000f0000
#define		PSASLPX_S_E_Y				0x00f00000
#define		PSASLPX_S_F_X				0x0f000000
#define		PSASLPX_S_F_Y				0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0	0x28c08
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1	0x28c0c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2	0x28c10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3	0x28c14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0	0x28c18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1	0x28c1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2	0x28c20
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3	0x28c24
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0	0x28c28
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1	0x28c2c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2	0x28c30
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3	0x28c34
#define PA_SC_AA_MASK_X0Y0_X1Y0			0x28c38
#define		PSAMXX_AA_MASK_X0Y0			0x0000ffff
#define		PSAMXX_AA_MASK_X1Y0			0xffff0000
#define PA_SC_AA_MASK_X0Y1_X1Y1			0x28c3c
#define		PSAMXX_AA_MASK_X0Y1			0x0000ffff
#define		PSAMXX_AA_MASK_X1Y1			0xffff0000

#define	VGT_VTX_REUSE_BLK_CTL			0x28c58
#define		VVRBC_VTX_REUSE_DEPTH			0x000000ff
#define	VGT_OUT_DEALLOC_CTL			0x28c5c
#define		VODC_DEALLOC_DIST			0x0000007f
#define	CB_0_COLOR_BASE				0x28c60
#define	CB_0_COLOR_PITCH			0x28c64
#define		CCP_TILE_MAX				0x000007ff
#define	CB_0_COLOR_SLICE			0x28c68
#define		CCS_TILE_MAX				0x003fffff
#define	CB_0_COLOR_VIEW				0x28c6c
#define		CCV_SLICE_START				0x000007ff
#define		CCV_SLICE_MAX				0x00ffe000
#define CB_0_COLOR_INFO				0x28c70
#define		CCI_ENDIAN				0x00000003
#define			CCI_ENDIAN_NONE				0
#define			CCI_ENDIAN_8IN16			1
#define			CCI_ENDIAN_8IN32			2
#define			CCI_ENDIAN_8IN64			3
#define		CCI_FMT					0x0000007c
#define			CCI_COLOR_INVALID			0
#define			CCI_COLOR_8				1
#define			CCI_COLOR_16				2
#define			CCI_COLOR_8_8				3
#define			CCI_COLOR_32				4
#define			CCI_COLOR_16_16				5
#define			CCI_COLOR_10_11_11			6
#define			CCI_COLOR_11_11_10			7
#define			CCI_COLOR_10_10_10_2			8
#define			CCI_COLOR_2_10_10_10			9
#define			CCI_COLOR_8_8_8_8			10
#define			CCI_COLOR_32_32				11
#define			CCI_COLOR_16_16_16_16			12
#define			CCI_COLOR_32_32_32_32			14
#define			CCI_COLOR_5_6_5				16
#define			CCI_COLOR_1_5_5_5			17
#define			CCI_COLOR_5_5_5_1			18
#define			CCI_COLOR_4_4_4_4			19
#define			CCI_COLOR_8_24				20
#define			CCI_COLOR_24_8				21
#define			CCI_COLOR_X24_8_32_FLOAT		22
#define		CCI_LINEAR_GENERAL			BIT(7)
#define		CCI_NUMBER_TYPE				0x00000700
#define			CCI_NUMBER_UNORM			0
#define			CCI_NUMBER_SNORM			1
#define			CCI_NUMBER_UINT				4
#define			CCI_NUMBER_SINT				5
#define			CCI_NUMBER_SRGB				6
#define			CCI_NUMBER_FLOAT			7
#define		CCI_COMP_SWAP				0x00001800
#define			CCI_SWAP_STD				0
#define			CCI_SWAP_ALT				1
#define			CCI_SWAP_STD_REV			2
#define			CCI_SWAP_ALT_REV			3
#define		CCI_FAST_CLR				BIT(13)
#define		CCI_COMPRESSION				BIT(14)
#define		CCI_BLEND_CLAMP				BIT(15)
#define		CCI_BLEND_BYPASS			BIT(16)
#define		CCI_SIMPLE_FLOAT			BIT(17)
#define		CCI_ROUND_MODE				BIT(18)
#define		CCI_CMASK_IS_LINEAR			BIT(19)
#define		CCI_BLEND_OPT_DONT_RD_DST		0x00700000
#define			CCI_FORCE_OPT_AUTO			0
#define			CCI_FORCE_OPT_DIS			1
#define			CCI_FORCE_OPT_ENA_IF_SRC_A_0		2
#define			CCI_FORCE_OPT_ENA_IF_SRC_RGB_0		3
#define			CCI_FORCE_OPT_ENA_IF_SRC_ARGB_0		4
#define			CCI_FORCE_OPT_ENA_IF_SRC_A_1		5
#define			CCI_FORCE_OPT_ENA_IF_SRC_RGB_1		6
#define			CCI_FORCE_OPT_ENA_IF_SRC_ARGB_1		7
#define		CCI_BLEND_OPT_DISCARD_PIXEL		0x01800000
#define			CCI_FORCE_OPT_AUTO			0
#define			CCI_FORCE_OPT_DIS			1
#define			CCI_FORCE_OPT_ENA_IF_SRC_A_0		2
#define			CCI_FORCE_OPT_ENA_IF_SRC_RGB_0		3
#define			CCI_FORCE_OPT_ENA_IF_SRC_ARGB_0		4
#define			CCI_FORCE_OPT_ENA_IF_SRC_A_1		5
#define			CCI_FORCE_OPT_ENA_IF_SRC_RGB_1		6
#define			CCI_FORCE_OPT_ENA_IF_SRC_ARGB_1		7
#define	CB_0_COLOR_ATTRIB			0x28c74
#define		CCA_TILE_MODE_IDX			0x0000001f
#define		CCA_FMASK_TILE_MODE_IDX			0x000003e0
#define		CCA_SAMPLES_N				0x00007000
#define		CCA_FRAGMENTS_N				0x00018000
#define		CCA_FORCE_DST_ALPHA_1			BIT(17)

#define CB_0_COLOR_CMASK			0x28c7c
#define		CCC_TILE_MAX				0x00003fff
#define CB_0_COLOR_FMASK			0x28c84
#define	CB_0_COLOR_FMASK_SLICE			0x28c88
#define		CCFS_TILE_MAX				0x003fffff

#define CB_0_COLOR_CLR_WORD_0			0x28c8c
#define	CB_0_COLOR_CLR_WORD_1			0x28c90

#define CB_1_COLOR_BASE				0x28c9c
#define CB_1_COLOR_PITCH			0x28ca0
#define CB_1_COLOR_SLICE			0x28ca4
#define CB_1_COLOR_VIEW				0x28ca8
#define CB_1_COLOR_INFO				0x28cac
#define CB_1_COLOR_ATTRIB			0x28cb0

#define CB_1_COLOR_CMASK			0x28cb8
#define CB_1_COLOR_CMASK_SLICE			0x28cbc
#define CB_1_COLOR_FMASK			0x28cc0
#define CB_1_COLOR_FMASK_SLICE			0x28cc4
#define CB_1_COLOR_CLR_WORD_0			0x28cc8
#define CB_1_COLOR_CLR_WORD_1			0x28ccc

#define CB_2_COLOR_BASE				0x28cd8
#define CB_2_COLOR_PITCH			0x28cdc
#define CB_2_COLOR_SLICE			0x28ce0
#define CB_2_COLOR_VIEW				0x28ce4
#define CB_2_COLOR_INFO				0x28ce8
#define CB_2_COLOR_ATTRIB			0x28cec

#define CB_2_COLOR_CMASK			0x28cf4
#define CB_2_COLOR_CMASK_SLICE			0x28cf8
#define CB_2_COLOR_FMASK			0x28cfc
#define CB_2_COLOR_FMASK_SLICE			0x28d00
#define CB_2_COLOR_CLR_WORD_0			0x28d04
#define CB_2_COLOR_CLR_WORD_1			0x28d08

#define CB_3_COLOR_BASE				0x28d14
#define CB_3_COLOR_PITCH			0x28d18
#define CB_3_COLOR_SLICE			0x28d1c
#define CB_3_COLOR_VIEW				0x28d20
#define CB_3_COLOR_INFO				0x28d24
#define CB_3_COLOR_ATTRIB			0x28d28

#define CB_3_COLOR_CMASK			0x28d30
#define CB_3_COLOR_CMASK_SLICE			0x28d34
#define CB_3_COLOR_FMASK			0x28d38
#define CB_3_COLOR_FMASK_SLICE			0x28d3c
#define CB_3_COLOR_CLR_WORD_0			0x28d40
#define CB_3_COLOR_CLR_WORD_1			0x28d44

#define CB_4_COLOR_BASE				0x28d50
#define CB_4_COLOR_PITCH			0x28d54
#define CB_4_COLOR_SLICE			0x28d58
#define CB_4_COLOR_VIEW				0x28d5c
#define CB_4_COLOR_INFO				0x28d60
#define CB_4_COLOR_ATTRIB			0x28d64

#define CB_4_COLOR_CMASK			0x28d6c
#define CB_4_COLOR_CMASK_SLICE			0x28d70
#define CB_4_COLOR_FMASK			0x28d74
#define CB_4_COLOR_FMASK_SLICE			0x28d78
#define CB_4_COLOR_CLR_WORD_0			0x28d7c
#define CB_4_COLOR_CLR_WORD_1			0x28d80

#define CB_5_COLOR_BASE				0x28d8c
#define CB_5_COLOR_PITCH			0x28d90
#define CB_5_COLOR_SLICE			0x28d94
#define CB_5_COLOR_VIEW				0x28d98
#define CB_5_COLOR_INFO				0x28d9c
#define CB_5_COLOR_ATTRIB			0x28da0

#define CB_5_COLOR_CMASK			0x28da8
#define CB_5_COLOR_CMASK_SLICE			0x28dac
#define CB_5_COLOR_FMASK			0x28db0
#define CB_5_COLOR_FMASK_SLICE			0x28db4
#define CB_5_COLOR_CLR_WORD_0			0x28db8
#define CB_5_COLOR_CLR_WORD_1			0x28dbc

#define CB_6_COLOR_BASE				0x28dc8
#define CB_6_COLOR_PITCH			0x28dcc
#define CB_6_COLOR_SLICE			0x28dd0
#define CB_6_COLOR_VIEW				0x28dd4
#define CB_6_COLOR_INFO				0x28dd8
#define CB_6_COLOR_ATTRIB			0x28ddc

#define CB_6_COLOR_CMASK			0x28de4
#define CB_6_COLOR_CMASK_SLICE			0x28de8
#define CB_6_COLOR_FMASK			0x28dec
#define CB_6_COLOR_FMASK_SLICE			0x28df0
#define CB_6_COLOR_CLR_WORD_0			0x28df4
#define CB_6_COLOR_CLR_WORD_1			0x28df8

#define CB_7_COLOR_BASE				0x28e04
#define CB_7_COLOR_PITCH			0x28e08
#define CB_7_COLOR_SLICE			0x28e0c
#define CB_7_COLOR_VIEW				0x28e10
#define CB_7_COLOR_INFO				0x28e14
#define CB_7_COLOR_ATTRIB			0x28e18

#define CB_7_COLOR_CMASK			0x28e20
#define CB_7_COLOR_CMASK_SLICE			0x28e24
#define CB_7_COLOR_FMASK			0x28e28
#define CB_7_COLOR_FMASK_SLICE			0x28e2c
#define CB_7_COLOR_CLR_WORD_0			0x28e30
#define CB_7_COLOR_CLR_WORD_1			0x28e34
#endif

